It is a general wish in the manufacture of integrated circuits to test these integrated circuits as to their functionality. Such tests can be carried out by means of external testing arrangements. In an external test, however, many production-related problems and high expenses occur owing to                the very high integration density of such integrated circuits,        the very high clock frequencies at which these integrated circuits operate, and        the very large number of test vectors required, which lead to complicated Very Large Scale Integration (VLSI) testing systems with large test vector memories.        
The prior-art publication U.S. Pat. No. 6,061,818, U.S. Pat. No. 6,671,838, U.S. Pat. No. 6,684,358, and US 2003/0140293 A1 disclose possibilities for realizing such test arrangements; additionally, reference is made to the publications DE 100 38 327 A1 and DE 101 10 777 A1 from the prior art.
The test arrangements disclosed in these publications, however, are not suitable inter alia for solving test problems which are caused substantially by high Integrated Circuit (IC) internal clock frequencies and Input Output (I/O) bond pad stages that are very slow in comparison with the former. The high internal clock frequencies of the integrated circuits have indeed an unfavorable ratio to the comparatively very slow input/output bond pad stages that lead to the exterior.
It is desirable for this reason to have available a kind of self-test of the integrated circuit. A self-test circuit is provided in that case within the integrated circuit, serving to test the application circuit also provided in the integrated circuit. The application circuit is that circuit that is designed for the actual practical purpose of the integrated circuit.
A first step in solving the above problems is the use of the so-termed Build-In Self-Test (BIST) method. Conventionally, the circuit is made better capable of random testing, for example by the insertion of test points, or a so-termed Bit-Flipping Function (BFF) is used.
The conventional implementation based on logic gates of the additional deterministic logic BIST hardware (the so-termed DLBIST hardware) here leads to a too large additional DLBIST hardware in practice with real, large integrated circuit arrangements.